Power Reduction in Wireless Receivers through Multistage Digital Filtering and Quantization
نویسنده
چکیده
The number of bits required to accurately represent a received signal in a wireless system changes as the out-of-band interference is removed by an IIR digital filter, if the filtering is done in stages, such as second-order sections. Taking advantage of this fact can reduce the size of the datapath in a VLSI realization of a digital filter, and hence power and area can be saved without decreasing performance. An effective algorithm for computing this reduced number of bits to use for quantization after each stage is derived, and a scheme for optimally ordering the second-order sections is presented. Power savings range from 33% to 50%, depending on the amount of out-ofband interference.
منابع مشابه
Optimal A/D Conversion Considerations and Results
Optimum scalar quantization is considered for the IIR filter and quantization system presented in "Power reduction in wireless receivers through multistage digital filtering and quantization" [1]. In [1], only suboptimum uniform quantization was used. An optimum scalar quantizer was constructed for a training sequence with a Signal to Interference ratio of −40dB, as was considered in extensivel...
متن کاملEnhancement of Noise Performance in Digital Receivers by Over Sampling the Received Signal
In wireless channel the noise has a zero mean. This channel property can be used in the enhancement of the noise performance in the digital receivers by oversampling the received signal and calculating the decision variable based on the time average of more than one sample of the received signal. The averaging process will reduce the effect of the noise in the decision variable that will approa...
متن کاملDecrease in Hardware Consumption and Quantization Noise of Digital Delta-Sigma Modulators and Implementation by VHDL
A new structure is presented for digital delta-sigma modulator (DDSM). Novel architecture decreases hardware consumption, output quantization noise and spurs in Comparison to previous architectures. In order to reduce the delay, power consumption and increase maximum working frequency, the pipelining technique and the carry skip adder are used. Simulation proposed architecture shows that the qu...
متن کاملAn ultra low power wake-up signal decoder for wireless nodes activation in Internet of Things technology
This paper proposes a new structure for digital address decoders based on flip-flops with application in wake-up signal generators of wireless networks nodes. Such nodes equipped with this device can be utilized in Internet of Things applications where the nodes are dependent on environment energy harvesting to survive for a long time. Different parts in these wireless nodes should have an e...
متن کاملPower Efficient Reconfigurable Fast Filter Bank for Multi-Standard Wireless Receivers
This brief presents a reconfigurable fast filter bank (RFFB) with less gate counts for wireless communication applications such as spectrum sensing and channelization. This is designed with an improved modified frequency transformation-based variable digital filter (MFTVDF) at the first stage of the multistage implementation. The low-pass MFT-VDF offers unabridged control over the cutoff freque...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 1999